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unisonic technologies co., ltd u74hc4046a cmos ic www.unisonic.com.tw 1 of 19 copyright ? 2013 unisonic technologies co., ltd qw-r502-461.c phase locked loop with vco ? description the u74hc4046a is a phase-locked-loop circuit including a linear voltage-controlled oscillator (vco), three different phase comparators (pc1, pc2 and pc3), a common signal input amplifier and a common comparator input. the signal can be directly coupled to large voltage signals or with a series capacitor coupled to small voltage signals. small voltage signals can be kept within the linear region of the input amplifiers with a self-bias input circuit. the u74hc4046a and a passive low-pass filter form a second-order loop pll. with a linear op-amp, the vco achieves excellent linearity. the vco requires an external capacitor and resistor. r1 (between r1 and gnd) and capacitor c1 (between c1a and c1b) determine the frequency range of the vco. r2 (between r2 and gnd) enables the vco to have a frequency offset if required. sop-16 tssop-16 for the high input impedance of the vc o, the design of low-pass filters is si mplified, and the designer has a wide choice of resistor/capacitor ranges. at pin 10 (dem out ), a demodulator output of the vco input voltage is provided in order not to load the low-pass filter . in conventional techniques, the dem out voltage is one threshold voltage lower than the vco input voltage, but the dem out voltage of u74hc4046 equals the vco input voltage. when dem out is used, a load resistor (rs) should be connected from dem out to gnd; but if unused, dem out should be left open. the vco output (vco out ) can be connected directly or via a frequency- divider to the comparator input (comp in ). if the vco input is held at a constant dc level, the vco output signal has a duty factor of 50% (maximum expected deviation 1%). a low level at the inhibit input (inh) enables the vco and demodulator, while a high level turns both off to minimize standby power consumption. ? features * low power consumption * operating power supply voltage range: digital section 2.0 to 6.0 v vco section 3.0 to 6.0 v * up to 17 mhz (typ.) centre frequency at v cc = 4.5 v * excellent vco frequency linearity * vco-inhibit control for on/off keying and for low standby power consumption * minimal frequency drift * three phase comparators: exclusive-or; edge-triggered jk flip-flop; edge-triggered rs flip-flop * zero voltage offset due to op-amp buffering * standard output capability * msi i cc category
u74hc4046a cmos ic unisonic technologies co., ltd 2 of 19 www.unisonic.com.tw qw-r502-461.c ? ordering information ordering number package packing lead free halogen free u74hc4046al-s16-r U74HC4046AG-S16-R sop-16 tape reel u74hc4046al-p16-r u74hc4046ag-p16-r tssop-16 tape reel
u74hc4046a cmos ic unisonic technologies co., ltd 3 of 19 www.unisonic.com.tw qw-r502-461.c ? pin configuration pcp out pc1 out comp in vco out inh c1a c1b gnd v cc pc3 out sig in pc2 out r2 r1 dem out vco in 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ? logic symbol ? iec symbol
u74hc4046a cmos ic unisonic technologies co., ltd 4 of 19 www.unisonic.com.tw qw-r502-461.c ? pin description pin no symbol function 1 pcp out phase comparator pulse output 2 pc1 out phase comparator 1output 3 comp in comparator input 4 vco out vco output 5 inh inhibit input 6 c1 a capacitor c1 connection a 7 c1 b capacitor c1 connection b 8 gnd ground 9 vco in vco input 10 dem out demodulator output 11 r1 resistor r1 connection 12 r2 resistor r2 connection 13 pc2 out phase comparator 2 output 14 sig in signal input 15 pc3 out phase comparator 3 output 16 v cc positive supply voltage
u74hc4046a cmos ic unisonic technologies co., ltd 5 of 19 www.unisonic.com.tw qw-r502-461.c ? functional diagram ? logic diagram
u74hc4046a cmos ic unisonic technologies co., ltd 6 of 19 www.unisonic.com.tw qw-r502-461.c ? absolute maximum ratings parameter symbol test conditions min typ max unit dc supply voltage v cc -0.5 +7 v dc input diode current i ik for v in < ? 0.5 v or v in > v cc + 0.5 v 20 ma dc output diode current i ok for v out < ? 0.5 v or v out > v cc + 0.5 v 20 ma dc output source or sink current i o for ? 0.5 v < v out < v cc + 0.5 v 25 ma dc vcc or gnd current i cc , i gnd 50 ma power dissipation per package plastic dil p d for temperature range: ? 40 to +125 c above +70 c: derate linearly with 12 mw/k 750 mw power dissipation per package plastic mini-pack(so) for temperature range: ? 40 to +125 c above +70 c: derate linearly with 8 mw/k 500 mw storage temperature range t stg -65 +150 c note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? recommended operating conditions parameter symbol test conditions min typ max unit dc supply voltage v cc 3.0 5.0 6.0 v dc supply voltage if vco section is not used v cc 2.0 5.0 6.0 v dc input voltage range v in 0 v cc v dc output voltage range v out 0 v cc v input rise and fall times (pin 5) t r , t f v cc = 2.0 v 6.0 1000 ns v cc = 4.5 v 6.0 500 ns v cc = 6.0 v 6.0 400 ns ambient operating temperature t opr see dc and ac characteristics -40 +85 c -40 +125 c ? quick reference data (gnd = 5v; t = 25 c) parameter symbol test conditions min typ max unit vco centre frequency f o c1 = 40 pf; r1 = 3 k ? ;v cc = 5v 19 mhz input capacitance (pin 5) c in 3.5 pf power dissipation capacitance per package c pd (note) 24 pf note : c pd is used to determine the dynamic power dissipation (p d in w): + = ) f v (c v c p o 2 cc l i 2 cc pd d f where: f i = input frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; f o =output frequency in mhz; ) v (c o 2 cc l f = sum of outputs.
u74hc4046a cmos ic unisonic technologies co., ltd 7 of 19 www.unisonic.com.tw qw-r502-461.c ? dc characteristics (t a =25c , unless otherwise specified) quiescent supply current (voltages are referenced to gnd (ground = 0 v)) parameter symbol test conditions min typ max unit quiescent supply current (vco disabled) i cc v cc =6.0v pins 3, 5 and 14 at v cc ; pin 9 at gnd; i in at pins 3 and 14 to be excluded 8.0 a phase comparator section parameter symbol test conditions min typ max unit dc coupled (high level input voltage sig in , comp in ) v ih v cc =2.0v 1.5 1.2 v v cc =4.5v 3.15 2.4 v cc =6.0v 4.2 3.2 dc coupled (low level input voltage sig in , comp in ) v il v cc =2.0v 0.8 0.5 v v cc =4.5v 2.1 1.35 v cc =6.0v 2.8 1.8 high level output voltage (pcp out , pc nout ) v oh v i =v ih or v il, - i out = 20 a v cc =2.0v 1.9 2.0 v v cc =4.5v 4.4 4.5 v cc =6.0v 5.9 6.0 high level output voltage (pcp out , pc nout) v oh v i =v ih or v il, v cc =4.5v, - i o = 4.0 ma 3.98 4.32 v v cc =6.0v ,- i o = 5.2 ma 5.48 5.81 low level output voltage (pcp out , pc nout ) v ol v i =v ih or v il, - i out = 20 a v cc =2.0v 0 0.1 v v cc =4.5v 0 0.1 v cc =6.0v 0 0.1 low level output voltage (pcp out , pc nout ) v ol v i =v ih or v il, v cc =4.5v , i o = 4.0 ma 0.15 0.26 v v cc =6.0v , i o = 5.2 ma 0.16 0.26 input leakage current (sig in , comp in ) i in v i = v cc or gnd v cc =2.0v 3.0 a v cc =3.0v 7.0 v cc =4.5v 18.0 v cc =6.0v 30.0 3-state (off-state current pc2 out ) i oz v out = v cc or gnd, v i =v ih or v il , v cc =6.0v 0.5 a input resistance (sig in , comp in ) r in v cc =3.0v v in at self-bias operating point; v i = 0.5v; (fig. 7) 800 k ? v cc =4.5v 250 k ? v cc =6.0v 150 k ? vco section (voltages are referenced to gnd (ground = 0 v)) parameter symbol test conditions min typ max unit high level input voltage inh v ih v cc =3.0v 2.1 1.7 v v cc =4.5v 3.15 2.4 v cc =6.0v 4.2 3.2 low level input voltage inh v il v cc =3.0v 1.3 0.9 v v cc =4.5v 2.1 1.35 v cc =6.0v 2.8 1.8 high level output voltage vco out v oh v i =v ih or v il, - i out = 20 a v cc =3.0v 2.9 3.0 v v cc =4.5v 4.4 4.5 v cc =6.0v 5.9 6.0 high level output voltage vco out v oh v i =v ih or v il v c c =4.5v, -i o ut = 4.0 ma 3.98 4.32 v v c c =6.0v, -i o ut = 5.2 ma 5.48 5.81 low level output voltage vco out v ol v i =v ih or v il, i out = 20 a v cc =3.0v 0 0.1 v v cc =4.5v 0 0.1 v cc =6.0v 0 0.1 low level output voltage vco out v ol v i =v ih or v il v cc =4.5v, i o ut = 4.0 ma 0.15 0.26 v v cc =6.0v, i o ut = 5.2 ma 0.16 0.26 low level output voltage c1 a , c1 b v ol v i =v ih or v il v cc =4.5v, i o ut = 4.0 ma 0.4 v v cc =6.0v, i out =5.2 ma 0.4 input leakage current(inh, vco in ) i in v cc =6.0v, v i =v cc or gnd 0.1 a
u74hc4046a cmos ic unisonic technologies co., ltd 8 of 19 www.unisonic.com.tw qw-r502-461.c ? dc characteristics(cont.) vco section (cont.) parameter symbol test conditions min typ max unit resistance range r1 v cc =3.0v 3.0 300 k ? v cc =4.5v 3.0 300 v cc =6.0v 3.0 300 r2 v cc =3.0v (note) 3.0 300 k ? v cc =4.5v 3.0 300 v cc =6.0v 3.0 300 capacitor range c1 v cc =3.0v 40 pf v cc =4.5v 40 v cc =6.0v 40 operating voltage range at vco in v vcoin v cc =3.0v over the range specified for r1; for linearity (fig10) 1.1 1.9 v v cc =4.5v 1.1 3.4 v cc =6.0v 1.1 4.9 note: the parallel value of r1 and r2 should be more than 2.7 k ? . optimum performance is achieved when r1 and/ or r2 are/is > 10 k ? . demodulator section (voltages are referenced to gnd (ground = 0 v)) parameter symbol test conditions min typ max unit resistor range r s v cc =3.0v at r s > 300 k ? the leakage current can influence v demout 50 300 k ? v cc =4.5v 50 300 v cc =6.0v 50 300 offset voltage vco in to v demout v off v cc =3.0v v i = v vcoin =1/2 v cc ; values taken over r s range 30 mv v cc =4.5v 20 v cc =6.0v 10 dynamic output resistance at dem out r d v cc =3.0v v demout = 1/2 v cc 25 ? v cc =4.5v 25 v cc =6.0v 25
u74hc4046a cmos ic unisonic technologies co., ltd 9 of 19 www.unisonic.com.tw qw-r502-461.c ? ac characteristics (t a =25c , unless otherwise specified) phase comparator section (gnd = 0 v; t r = t f =6ns; c l = 50pf) parameter symbol test conditions min typ max unit propagation delay sig in , comp in to pcp out t phl / t plh v cc =2.0v fig.8 96 340 ns v cc =4.5v 35 68 v cc =6.0v 28 58 propagation delay sig in , comp in to pc3 out t phl / t plh v cc =2.0v fig.8 77 270 ns v cc =4.5v 28 54 v cc =6.0v 22 46 3-state output enable time sig in , comp in to pc2 out t pzh / t pzl v cc =2.0v fig.9 83 280 ns v cc =4.5v 30 56 v cc =6.0v 24 48 3-state output disable time sig in , comp in to pc2 out t phz / t plz v cc =2.0v fig.9 99 325 ns v cc =4.5v 36 65 v cc =6.0v 29 55 output transition time t phz / t plz v cc =2.0v fig.8 19 75 ns v cc =4.5v 7 15 v cc =6.0v 6 13 ac coupled input sensitivity (peak-to-peak value) at sig in or comp in v in(p-p) v cc =2.0v f i = 1mhz 9 mv v cc =3.0v 11 v cc =4.5v 15 v cc =6.0v 33 vco section (gnd = 0 v; t r = t f = 6 ns; c l = 50 pf) parameter symbol test conditions min typ max unit frequency stability with temperature change f/t v cc =3.0v v in = v vcoin = 1/2 v cc ; r1 = 100 k ? ; r2 = ; c1= 100 pf %/k v cc =4.5v v cc =6.0v vco centre frequency (duty factor = 50%) f o v cc =3.0v v vcoin = 1/2 v cc ; r1 = 3 k ? ;r2 = ; c1 = 40 pf 7.0 10.0 mhz v cc =4.5v 11.0 17.0 v cc =6.0v 13.0 21.0 vco frequency linearity f vco v cc =3.0v r1 = 100 k ? ; r2 = ; c1 = 100 pf;(fig.10) 1.0 % v cc =4.5v 0.4 v cc =6.0v 0.3 duty factor at vco out vco v cc =3.0v 50 % v cc =4.5v 50 v cc =6.0v 50
u74hc4046a cmos ic unisonic technologies co., ltd 10 of 19 www.unisonic.com.tw qw-r502-461.c ? phase comparators if the signal swing is between the standard hc family input logic levels, the signal input (sig in ) can be directly coupled to the self-biasing amplifier at pin 14. capacitive coupling is required for signals with smaller swings. phase comparator 1 (pc1) this is an exclusive-or network. to obtain the maxi mum locking range, the signal and comparator input frequencies (f i ) must have a 50% duty factor. the transfer characteristic of pc1, assuming ripple (f r = 2f i ) is suppressed, is: ) ( v v compin sigin demout cc ? = where v demout is the demodulator output at pin 10; v demout = v pc1out (via low-pass filter). the phase comparator gain is: ) r v / ( v k cc p = as shown in fig.1, the aver age output voltage from pc1, fed to the vc o input via the low-pass filter and seen at the demodulator output at pin 10 (v demout ) is the resultant of the phase differences of signals (sig in ) and the comparator input (comp in ). the average of v demout is equal to v cc /2 when there is no signal or noise at sig in and with this input the vco osc illates at the centre frequency (f o ). as shown in fig.2 it is the typical waveforms for the pc1 loop locked at f o . sig in comp in vco out pc1 out vco in v cc gnd fig.2 typical waveforms for pll using phase comparator 1, loop locked at f o . the frequency capture range (2f c ) is he frequency range of input signals on which the pll will lock if it was initially out-of-lock. the frequency lock range (2f l ) is the frequency range of input signals on which the loop will stay locked if it was initially in lock. the capture range is smaller or equal to the lock range. with pc1, the low-pass filter charac teristics determine the capture range which can be made as large as the lock range. this configuration retains lock even with very noisy input signals. typical behavior of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the vco centre frequency.
u74hc4046a cmos ic unisonic technologies co., ltd 11 of 19 www.unisonic.com.tw qw-r502-461.c ? phase comparators (cont.) phase comparator 2 (pc2) this is a positive edge-triggered phase and frequency detect or. if the pll is using the comparator, the loop is controlled by positive signal transit ions and the duty factors of sig in and comp in are not important. pc2 is comprised of two d-type flip-flops, control-gating and a 3- state output stage. t he circuit function is as an up-down counter (logic diagram) for sig in causes an up-count and comp in causes a down-count. the transfer function of pc2, assuming ripple (f r = f i ) is suppressed, is ) ( 4 v v compin sigin demout cc ? = where v demout is the demodulator output at pin 10; v demout = v pc2out (via low-pass filter). the phase comparator gain is: ) r v / ( 4 v k cc p = as shown in fig.3, v demout is the resultant of the in itial phase differences of sig in and comp in . typical waveforms for the pc2 loop locked at f o are shown in fig.4. 4 fig.3 phase comparator 2: average output voltage versus input phase difference. fig.4 typical waveforms for pll using phase comparator 2, loop locked at f o . if the frequencies of sig in and comp in are equal but the phase of sig in leads that of comp in , the p-type output driver at pc2 out is held ?on? for a time corresponding to the phase difference ( demout ). if the phase of sig in lags that of comp in , the n-type driver is held ?on?. if the frequency of sig in is higher than that of comp in , the p-type output driver is held ?on? for most of the input signal cycle time, and for the remainder of the cy cle both n and p-type drivers are ?off? (3-state). if the frequency of sig in is lower than that of comp in , the n-type driver that is held ?o n? for most of the cycle. then the voltage at the capacitor (c2) of the low-pass filter connected to pc2 out varies until the signal and comparator inputs are equal in both phase and frequency. at this stable state the voltage on c2 re mains constant as the pc2 output is in 3-state and the vco input at pin 9 is a high impedance. also in the conditi on, the signal at the phase comparator pulse output (pcp out ) is a high level, and it indicates a locked condition. for pc2, there is no phase difference between sig in and comp in over the full frequency range of the vco. and as the low-pass filter, the power dissipation is reduced because both p and n-type drivers are ?off? for most of the signal input cycle. it should be noted that the pll lock range for this type of phase comparator is equal to the capture range and this is independent of the low-pass filter. the vco adjusts to its lowest frequency via pc2 when no signal present at sig in .
u74hc4046a cmos ic unisonic technologies co., ltd 12 of 19 www.unisonic.com.tw qw-r502-461.c ? phase comparators (cont.) phase comparator 3 (pc3) this is a positive edge-triggered sequential phase detector using an rs-type flip-flop. if this comparator is used, the loop is controlled by positive signal transitions and the duty factors of sig in and comp in are not important. the transfer characteristic of pc3, assuming ripple (f r = f j ) is suppressed, is: ) ( 2 v v compin sigin demout cc ? = where v demout = v pc3out (via low-pass filter). the phase comparator gain is: ) r v / ( 2 v k cc p = as shown in fig.5, the average output voltage from pc3, fed to the low- pass filter and seen at the demodulator output at pin 10 (v demout ), is the resultant of t he phase differences of sig in and comp in . as shown in fig.6, it is the typical waveforms for the pc3 loop locked at f o . v cc v demout (av) 1/2v cc 0 demout 0 360 180 v demout =v pc3out = v cc ( sigin - compin ) demout = ( sigin - compin ) 2 fig.5 phase comparator 3: average output voltage versus input phase difference. fig.6 typical waveforms for pll using phase comparator 3, loop locked at f o . the phase-to-output response characteri stic of pc3 (fig.5) differs from that of pc2, as the phase angle between sig in and comp in varies between 0 o and 360 o and 180 o is the centre frequency. and the voltage swing of pc3 is greater than that of pc2 for input phase differences, but as a cons equence the ripple cont ent of vco input signal is higher. both of the pll lock range and capture range of this type of phase comparator are dependent on the low-pass filter. the vco adjusts to its lowest frequency via pc3, when no signal present at sig in .
u74hc4046a cmos ic unisonic technologies co., ltd 13 of 19 www.unisonic.com.tw qw-r502-461.c ? figure references for dc characteristics self-bias operating point v in i in v in fig.7 typical input resistance curve at sig in , comp in .
u74hc4046a cmos ic unisonic technologies co., ltd 14 of 19 www.unisonic.com.tw qw-r502-461.c ? ac waveforms sig in , comp in v m v m t phl t plh pcp out pc1 out pc3 out t tlh t thl v m = 50%, v h = 90%, v l = 10% fig.8 waveforms showing input (sig in , comp in ) to output (pcp out , pc1 out , pc3 out ) propagation delays and the output transition times. fig.9 waveforms showing the 3-state enable and disable times for pc2 out . fig.10 definition of vco frequency linearity: ? v = 0.5 v over the vcc range: for vco linearit y f? 0 = (f 1 +f 2 )/2, linearity (f? 0 +f 0 )/f? 0 100%
u74hc4046a cmos ic unisonic technologies co., ltd 15 of 19 www.unisonic.com.tw qw-r502-461.c ? application information this is a reference for the values of external components to be used with the u74hc4046a in a pll system. the ranges of the val ues of the components: vco frequency without extra offset (phase comparator: pc1, pc2 or pc3) frequency characteristic: with r2 = and r1 between 3 k ? and 300 k ? , the characteristics of the vco operation will be as shown in fig.11 (due to r1, c1 time constant a small offset remains when r2 = ). fig.11 frequency characteristic of vco operating without offset: f 0 = centre frequency; 2f l = frequency lock range. component value r1 3 k ? ~ 300 k ? r2 3 k ? ~ 300 k ? d r1+r2 parallel value > 2.7 k ? c1 greater than 40 pf
u74hc4046a cmos ic unisonic technologies co., ltd 16 of 19 www.unisonic.com.tw qw-r502-461.c ? application information(cont.) vco frequency with extra offset (phase comparator: pc1, pc2 or pc3) frequency characteristic: with r1 and r2 between 3 k ? and 300 k ? , the characteristics of the vco oper ation will be as shown in fig.12. due to r1, c1 f vco f max f 0 f min ? v cc v cc ?0.9v v cc vco in 0.9v 2f l f off due to r2, c1 fig.12 frequency characteristic of vco operating with offset: f 0 = centre frequency; 2f l = frequency lock range. pc1, pc2 or pc3 selection of r1, r2 and c1 given f o and f l , determine the value of r1 c1 calculate f off from the equation f off = f o ? 1.6f l obtain the values of c1 and r2 calculate the value of r1 fr om the value of c1 and r1 c1. subject phase comparator design considerations pll conditions with no signal at the sig in input pc1 vco adjusts to f o with demout = 90 and v vconin = 1/2 v cd (fig.1). pc2 vco adjusts to f o with demout = -360 and v vconin = min. (fig.3). pc3 vco adjusts to f o with demout = -360 and v vconin = min. (fig.5).
u74hc4046a cmos ic unisonic technologies co., ltd 17 of 19 www.unisonic.com.tw qw-r502-461.c ? application information(cont.) pll frequency capture range (phase comparator: pc1, pc2 or pc3) loop filter component selection j a small capture range (2f c ) is obtained if / f 2 1 f 2 l c fig.13 simple loop lter for pll without offset; r3 500 ? . r3 c2 input output 1/ 3 m ) ( f j (b) amplitude characteristic (c) pole-zero diagram + = fig.14 simple loop lter for pll with offset; r3 + r4 500 ? . subject phase comparator design considerations pll locks on harmonics at centre frequency pc1 or pc3 yes pc2 no noise rejection at signal input pc1 high pc2 or pc3 low ac ripple content when pll is locked pc1 f r = 2f i , large ripple content at demout = 90 pc2 f r = f i , small ripple content at demout = 0 pc3 f r = f i , large ripple content at demout = 180
u74hc4046a cmos ic unisonic technologies co., ltd 18 of 19 www.unisonic.com.tw qw-r502-461.c ? pll design example fig.15 frequency synthesizer. the parameters of the frequenc y synthesizer in fig.15: output frequency: 2 mhz to 3 mhz frequency steps: 100khz settling time: 1ms overshoot: < 20% the open-loop gain is: n o f p k k k k s g s h = ) ( ) ( where: k p = phase comparator gain k f = low-pass filter transfer gain k o = k v /s vco gain k n = 1/n divider ratio the programmable counter ratio k n can be found as follows: 20 100khz 2mhz f f n step out min = = = 0 3 100khz 3mhz f f n step out max = = = the vco is set by the values of r1, r2 and c1, r2 = 10 k ? (adjustable). the values can be determined using the information in the section ?design considerations?. with f o = 2.5mhz and f l =500 khz this gives the following values (v cc = 5.0 v): r1 = 10 k ? ; r2 = 10 k ? ; c1 = 500 pf the vco gain is: / v s / r 10 2 2 3.2 1mhz 0.9) (v 0.9 2 2f k 6 cc l v = ? ? = the gain of the phase comparator is: s 0.4v / 4 v k cc p = = the transfer gain of the filter is given by: s ) ( 1 s 1 k 2 1 2 f + + + = where: r3c2 1 = and r4c2 2 = the characteristics equation is: 1 + h(s) g(s) = 0 this results in: 0 ) ( k k k s ) ( 1 s 2 1 n v p 2 1 2 2 = + + + + + n v p k k k the natural frequency n is defined as follows: ) ( 2 1 + = n v p n k k k damping value is defined as follows: ) ( 1 2 1 2 1 2 + + = n v p n k k k
u74hc4046a cmos ic unisonic technologies co., ltd 19 of 19 www.unisonic.com.tw qw-r502-461.c utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.

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